Adaptive tuning circuit to maximize output signal amplitude for an amplifier

ABSTRACT

An adaptive tuning circuit to maximize the output signal amplitude of a band-pass amplifier, comprising a control circuit to tune the peak frequency of the amplifier by monitoring the change in the output signal amplitude over two successive time sampling intervals. In some embodiments, the control circuit comprises an envelope detector and a switched capacitor circuit to provide voltages indicative of the difference in the output signal amplitude over two successive time intervals. Other embodiments are described and claimed.

FIELD

Embodiments of the present invention relate to electronic circuits, and more particularly, to adaptive tuning circuits for tuning band-pass amplifiers.

BACKGROUND

Band-pass amplifiers are used in a wide variety of electronic systems. In particular, inductor-load amplifiers may be used to receive and amplify narrow band clock signals in high-speed serial input-output communication links. It is desirable for the peak of the response of the amplifier to match the center frequency of the narrow band clock signal. However, the peak of the response may depend upon the inductance of the inductor-load, as well as the capacitance of capacitors connected in parallel with the inductor-load. Accordingly, once a band-pass amplifier has been fabricated in an integrated circuit process technology, it would be useful to provide a control circuit to adaptively tune the band-pass amplifier when used in a system, so as to match the center frequency of a received narrow band clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a illustrates some embodiments of the present invention.

FIG. 1 b illustrates the relative timing diagrams of three clock signals used in the embodiments of FIG. 1 a.

FIG. 2 illustrates in more detail an embodiment of the tunable band-pass amplifier in the embodiments of FIG. 1 a.

FIG. 3 illustrates in more detail an embodiment of the sampler circuit in the embodiments of FIG. 1 a.

FIG. 4 illustrates in more detail an embodiment of the envelope detector in the embodiments of FIG. 1 a.

FIG. 5 illustrates an application of some embodiments of the present invention to a computer system.

DESCRIPTION OF EMBODIMENTS

In the descriptions that follow, the scope of the term “some embodiments” is not to be so limited as to mean more than one embodiment, but rather, the scope may include one embodiment, more than one embodiment, or perhaps all embodiments.

FIG. 1 a is a high-level abstraction representing some embodiments of the present invention, and depicts a control loop for tuning amplifier 102. Amplifier 102 is a tunable band-pass amplifier. A control loop comprising control circuit 108 and finite state machine 110 tunes amplifier 102. For some embodiments, tuning is accomplished by changing the reactance of a load in amplifier 102, which may be realized by switching in or switching out various capacitive circuits in the reactive load. For other embodiments, tuning of amplifier 102 may be accomplished by changing various bias currents, or perhaps other parameters, of amplifier 102.

Finite state machine 110 has a set of states, and as it sequences through states in the set of states, amplifier 102 is tuned. For some embodiments, finite state machine 110 may comprise a counter having a counter value. For some embodiments, the counter initially counts down from its maximum counter value. Each time its counter value is decremented by one, a capacitive circuit is switched out, and amplifier 102 is tuned so that its peak frequency is shifted higher. Peak frequency refers to the band-pass center frequency of amplifier 102, that is, the frequency for which the transfer function of amplifier 102 has a maximum absolute value.

Amplifier 102 receives a differential input signal at input ports 104 a and 104 b to provide a differential output signal at its output ports 106 a and 106 b. While tuning amplifier 102, control circuit 108 samples the amplitude of the differential output signal. For some embodiments, if control circuit 108 detects that the amplitude has decreased from one time interval to the next, then finite state machine 110 is disabled so that tuning of amplifier 102 stops.

In applications where amplifier 102 amplifies a differential clock signal, control circuit 108 disables finite state machine 110 if it detects that tuning has caused the peak frequency to shift past the frequency of the differential clock signal. In this way, it is expected that if the various reactance values available for tuning are properly chosen, amplifier 102 will be tuned so that its peak frequency is close to that of the received clock frequency.

FIG. 2 provides a circuit representation of amplifier 102 according to some embodiments. Amplifier 102 comprises a differential pair, transistors 202 a and 202 b, with a tail current provided by transistor 204. The gate of transistor 204 is biased by a voltage V_(BIAS). A reactive load comprising inductor L and a set of capacitive circuits C_(j) loads the drains of the differential pair, where j is an index ranging over the integers 0, 1, . . . , n-1. Switching in or switching out capacitive circuits C_(j) tunes amplifier 102.

Inductor L may in practice comprise two or more discrete inductors. For simplicity, the circuit diagram of FIG. 2 shows inductor L as a center-tapped inductor, but for some embodiments, there may be one inductor coupling one drain of the differential pair to the drain of transistor 208 and a second inductor coupling the other drain of the differential pair to the drain of transistor 208.

A set of control voltages, [b_(n-1), b_(n-2), . . . , b₀] switches in or switches out various capacitive circuits in the set of capacitive circuits C_(j), where the control voltage b_(j) is associated with capacitive circuit C_(j) for each j=0, 1, . . . , n−1. Each capacitive circuit C_(j) comprises two capacitors, one connected to one drain of the differential pair and the other connected to the other drain of the differential pair. For b_(j) HIGH, its associated capacitive circuit C_(j) is switched in so that each capacitor in capacitive circuit C_(j) has a terminal connected to ground (or substrate) 206 via a switch, such as a nMOSFET (n-Metal Oxide Semiconductor Field Effect Transistor) that is switched ON.

The control voltage b_(j) effectively switches in or switches out its associated capacitive circuit C_(j). When a capacitive circuit is switched in, a first capacitor within the capacitive circuit is effectively connected in parallel with a first inductive load connected to a first drain of the differential pair, and a second capacitor is effectively connected in parallel with a second inductor connected to a second drain of the differential pair. By switching out more capacitive circuits, the peak frequency (band-pass center frequency) of amplifier 102 shifts higher, whereas by switching in more capacitive circuits, the peak frequency shifts lower.

The particular subset of the set of capacitive circuits that are adaptively switched out is determined by the state of finite state machine 110. As an example, suppose finite state machine 10 comprises a counter where the state is the value of the counter. Let c denote the counter value of counter, and write the set of control voltages [b_(n-1), b_(n-2), . . . , b₀] as [ b _(H) b _(L)], where b _(L) is a vector of dimension m where m≦n. For those embodiments for which finite state machine 110 is realized by a counter, the vector b _(L) is set by the counter by establishing a correspondence between the counter value c and b _(L).

This correspondence may be designed in a number of ways. For example, a thermometer encoder may be used to encode the counter value c into a set of m logic voltages, where the counter value is a M bit word where 2^(M)=m. The encoding may be chosen such that initially each [ b _(L)]_(j), j=0, 1, . . . , m−1, is HIGH, and when the counter is enabled to start counting down, each time the counter value decrements, [ b _(L)]_(j) is brought LOW where c=j. If the counter is decremented all the way to zero, then each [ b _(L)]_(j), j=0, 1, . . . , m−1, would have been brought LOW, and all capacitive circuits would have been switched out.

The subscripts H and L for b _(H) and b _(L) provide the mnemonic that b _(H) represents the higher indexed voltages in the set [b_(n-1), b_(n-2), . . . , b₀] and b _(L) represents the lower indexed voltages. The higher indexed voltages b _(H) may be chosen by any method, and may be set in a non-adaptive fashion. For some embodiments, the control voltages may be chosen such that choosing the higher indexed voltages b _(H) sets the band of frequencies over which amplifier 102 is tuned. Note that b _(H) may be the null vector if m=n, in which case all of the voltages [b_(n-1), b_(n-2), . . . , b₀] are adaptively controlled by the control loop.

Control circuit 108 in the embodiment illustrated in FIG. 1 a comprises envelope detector 112, sampler circuit 114, and comparator 116. Representing the differential output signal of amplifier 102 as the differential small-signal voltage {v_(P)(t) v_(N)(t)}, envelope detector 112 provides a differential small-signal envelope {e_(P)(t) e_(N)(t)} approximately given by e_(P)(t)=LP{|v_(P)(t)|} and e_(N)(t)=−LP{|v_(N)(t)|}, where LP denotes low pass filtering. The amplitude, a(t), of the differential output signal of amplifier 102 may be defined as a(t)=e_(P)(t)−e_(N)(t). Sampler circuit 114 effectively samples the amplitude a(t) over two consecutive time intervals. If the amplitude a(t) decreases from one sampling time interval to the next, then control circuit 108 provides a signal to disable finite state machine 110.

Three clock signals, a reset signal φ₁, a pre-charge signal φ₂, and an evaluate signal φ₃, are utilized in the embodiment of FIG. 1 a. FIG. 1 b shows the relative timing for these three clock signals. FIG. 3 illustrates sampler circuit 114 in more detail, and how the reset and evaluate clock signals are utilized by sampler circuit 114. Referring to FIG. 3, sampler circuit 114 is a switched capacitor circuit comprising sampling capacitors 302 a and 302 b, inverters 304 a and 304 b, switches 306 a and 306 b that are closed when the reset signal φ₁ is HIGH, and switches 308 a and 308 b that are closed when the evaluate signal φ₃ is HIGH.

As FIG. 1 b shows, during one complete cycle the reset signal will go from LOW to HIGH to LOW, after which the pre-charge signal will go from LOW to HIGH to LOW, and after which the evaluate signal will go from LOW to HIGH to LOW. When the reset signal φ₁ is HIGH, switches 306 a and 306 b close so that the output port of inverter 304 a is connected to its input port, and the output port of inverter 304 b is connected to its input port. When switch 306 a is closed, node 310 a settles to some voltage V₀, the voltage for which the output voltage of inverter 304 a is equal to its input voltage. Similarly, when switch 306 b is closed, node 310 b settles to some voltage V₀′, the voltage for which the output voltage of inverter 304 b is equal to its input voltage. Preferably, inverters 304 a and 304 b should be matched so that the voltages V₀ and V₀′ are sufficiently close to each other.

During a reset time interval for which the reset signal is HIGH, capacitor 302 a stores a charge Q approximately given by Q=C(e_(P)(t₀)−V₀)+Q₀, where C is the capacitance of capacitor 302 a, e _(P)(t₀) is the small-signal voltage envelope at output port 312 a at some time t₀ within the reset time interval, and Q₀ is some fixed charge due to the common-mode voltage of output port 312 a. In a sense, the information represented by e_(P)(t₀) is stored in capacitor 302 a. Similarly, capacitor 302 b stores a charge Q′ approximately given by Q′=C(e_(N)(t₀)−V₀′)+Q₀, where e_(N)(t₀) is the small-signal voltage envelope at output port 312 b at time t₀.

In the expressions for Q and Q′, for simplicity the capacitance of capacitor 302 b is taken to be equal to that of capacitor 302 a, and the common-mode voltages for output ports 312 a and 312 b are taken to be equal, although these are not requirements. Also, the typical convention for distinguishing small-signal voltages from actual voltages is followed, where the variable for a small-signal voltage is lower case and the variable for the actual corresponding voltage is upper case. For example, referring to FIG. 3, the envelope at output port 312 a for some arbitrary time t is denoted as E_(p)(t), whereas the corresponding small-signal envelope is written as e_(p)(t).

After the reset signal goes LOW, the pre-charge signal φ₂ goes HIGH, causing finite state machine 110 to change state, provided it has not been disabled. For some embodiments, finite state machine 110 is a counter in which it counts down when the pre-charge signal φ₂ goes HIGH, provided it has not been disabled.

During the pre-charge time interval, all switches shown in FIG. 3 are open. In the approximation that the input impedances of inverters 304 a and 304 b may be taken as infinite, nodes 310 a and 310 b are floating so that the charges on capacitors 302 a and 302 b do not change, in which case the voltages at nodes 310 a and 310 b move up or down depending upon the new values of e_(p)(t) and e_(N)(t) during the pre-charge time interval. That is, for constant charge, the following approximately holds: Q=C(e_(P)(t₀)−V₀)+Q₀=C(e_(P)(t₁)−V(node310 a))+Q₀, where t₁ is now some time value within the pre-charge time interval, and V(node310 a) denotes the voltage at node 310 a at the end of the pre-charge time interval. From this expression, it is seen that the voltage at node 310 a at the end of the pre-charge time interval is given approximately by e_(P)(t₁)−e_(P)(t₀)+V₀, so that the voltage at node 310 a is indicative of the change in the small-signal voltage envelope e_(P)(t) at output port 312 a from the reset time interval to the pre-charge time interval.

Similarly, the voltage at node 310 b at the end of the pre-charge time interval is given approximately by e_(N)(t₁)−e_(N)(t₀)+V₀′, so that the voltage at node 310 b is indicative of the change in the small-signal voltage envelope e_(N)(t) at output port 312 b from the reset time interval to the pre-charge time interval.

During the evaluate time interval, switches 308 a and 308 b are closed, so that inverters 304 a and 304 b are cross-coupled. For the case in which the amplitude a(t) has increased from the time reset time interval to the pre-charge time interval, a(t₁)>a(t₀), the voltage at node 310 a is |a(t₁)−a(t₀)| above V₀, the trip-threshold point for inverter 304 a, and the voltage at node 310 b is |a(t₁)−a(t₀)| below V₀′, the trip-threshold point for inverter 304 b. Cross-coupled inverters 304 a and 304 b amplify this difference so that node 314 a is brought towards LOW and node 314 b is brought towards HIGH.

Comparator 116 is clocked by the evaluate clock signal φ₃ so that finite state machine 110 ignores the output of sampler circuit 114 except during the evaluate time interval. Comparator 116 helps ensure that the signal provided to finite state machine 110 is at a full logic level. For the above case in which the amplitude a(t) has increased from the time reset time interval to the pre-charge time interval, the signal provided by comparator 116 is LOW, and the interface between finite state machine 110 and comparator 116 is designed so that finite state machine 110 is enabled for a LOW control signal.

For the case in which the amplitude a(t) has decreased from the time reset time interval to the pre-charge time interval, a(t₁)<a(t₀), the voltage at node 310 a is |a(t₁)−a(t₀)| below V₀ and the voltage at node 310 b is |a(t₁)−a(t₀)| above V₀′. Cross-coupled inverters 304 a and 304 b amplify this difference so that node 314 a is brought towards HIGH and node 314 b is brought towards LOW. Comparator 116 provides a HIGH signal to finite state machine 110, and the interface between finite state machine 110 and comparator 116 is designed so that finite state machine 110 is disabled for a HIGH control signal.

Envelope detector 112 may be implemented in a number of ways. An example of an embodiment is shown in FIG. 4, where the input ports are denoted as IN_(N) and IN_(P), and output ports 312 a and 312 b provide, respectively, the voltages E_(P)(t) and E_(N)(t). The circuit of FIG. 4 comprises four so-called Gilbert multipliers: transistors 402 and 404, transistors 406 and 408, transistors 410 and 404, and transistors 412 and 408.

Transistors 402 and 404 form a multiplier to sink a current at node 414 proportional to the square of the voltages on the gates of transistors 402 and 404. With capacitor 416 coupling the gate of transistor 404 to input port IN_(N), the small-signal current sunk at node 414 by the multiplier comprising transistors 402 and 404 is proportional to the square of the small-signal voltage at input port IN_(N). Transistors 406 and 408 form a multiplier to also sink current at node 414, but where the small-signal current is proportional to the square of the small-signal voltage at input port IN_(P). These small-signal currents add at node 414. Diode-connected transistor 418 provides a voltage at node 414 proportional to the square root of the current sunk at node 414. As a result, after applying low pass filter 420, the voltage envelope E_(N)(t) is provided at output port 312 b.

Transistors 410 and 404 form a multiplier to sink at node 422 a small-signal current proportional to the multiplication of the small-signal voltages on input port IN_(P) and input port IN_(N), and transistors 412 and 408 form a multiplier to sink at node 422 a small-signal current proportional to the multiplication of the small-signal voltages on input port IN_(N) and input port IN_(P). With diode-connected transistor 424 providing a voltage at node 422 proportional to the square of the current sunk at node 422, and low pass filter 426 providing a low pass filtering function to node 422, the voltage envelope E_(P)(t) is provided at output node 312 a.

Transistors 404 and 408 have their gates DC biased at a bias voltage V_(BIAS), so that transistor 404 provides a DC tail current to transistors 402 and 410, and transistor 408 provides a DC tail current to transistors 406 and 412.

One particular application of the above-described embodiments is for the amplification of a clock signal communicated from one module to another module via a communication link, such as a point-to-point interconnect or bus. Such a communication link may generally be viewed as a transmission line. As one example, FIG. 5 illustrates a portion of a computer system comprising microprocessor 502, chipset 504, and system memory 506. FIG. 5 is a simplification of a computer system, and in practice, other functional units are most likely employed. Furthermore, some computer systems may employ more than one microprocessor. Some of the functional units in FIG. 5 may be realized by more than one discrete chip. For example, memory 506 may represent a hierarchy of memory functional units, and chipset 504 may be realized by more than one discrete chip. Embodiments of the present invention, represented as embodiment 1 in FIG. 5, may reside in chipset 504, as well as other functional units.

In the example of FIG. 5, driver 508 drives transmission line 510 with a differential clock signal, received by receiver 512, providing the received differential signal to embodiment 1. Embodiments of the present invention may find applications to other systems, and to signals other than clock signals.

Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below. For example, various actions performed in the embodiments were described depending upon whether various nodes or ports were brought LOW or HIGH. However, these are often merely conventions, and various logic circuits may be designed so that the described actions occur for the complementary case in which a LOW voltage is substituted for a HIGH voltage and a HIGH voltage is substituted for a LOW voltage.

As a particular example, comparator 116 may be designed so that for the case in which the amplitude a(t) has increased from the time reset time interval to the pre-charge time interval, a(t₁)>a(t₀), comparator 116 provides a HIGH signal to finite state machine 110, and an interface circuit between finite state machine 110 and comparator 116 may be designed so that finite state machine 110 is enabled for a HIGH signal. This may be generalized by viewing comparator 116 as providing a Boolean voltage level when the difference in amplitudes a(t₁)−a(t₀) satisfies an ordered relationship with zero, where for some embodiments the Boolean voltage level may be HIGH and the ordered relationship may be >.

As another example, for some embodiments in which finite state machine 110 is a counter, finite state machine 110 may be incremented rather than decremented, so that capacitive circuits are sequentially switched in rather than switched out. In some embodiments, finite state machine 110 may be a counter that is decremented as described earlier, but where capacitive circuits are sequentially switched out rather than switched in. This merely involves designing various interface circuits between finite state machine 110 and amplifier 102. Stated in other words, different correspondences between the state of finite state machine 110 and the set of control voltages b _(L) may be designed. The use of a thermometer encoder described earlier is merely one example of designing such a correspondence.

In other variations in the embodiments, the duals to various circuits may be employed, as is well known in the art of circuit design, where nMOSFETs are substituted for pMOSFETs, and pMOSFETs are substituted for nMOSFETs. For example, for amplifier 102, pMOSFETs rather than nMOSFETS may be used for a differential pair.

Other embodiments may utilize other types of digitally controlled tunable band-pass amplifiers than the one illustrated in FIG. 2. The embodiment of FIG. 2 is an example of a tunable band-pass amplifier in which tuning is achieved by digitally changing the reactance of its load by switching in various capacitors. However, other tunable band-pass amplifiers may be employed, where the peak frequency is tuned in a manner different from the particular embodiment of FIG. 2. For example, digitally controlled current sources, or current mirrors, may be used to change various bias currents in an amplifier so as to tune its peak frequency. Accordingly, the scope of the claims below are not necessarily limited to tunable band-pass amplifiers having a tunable reactive load, but may encompass other types of amplifiers having a tunable peak frequency that is digitally controlled.

It is to be understood in these letters patent that the meaning of “A is connected to B”, where A or B may be, for example, a node or device terminal, is that A and B are connected to each other so that the voltage potentials of A and B are substantially equal to each other. For example, A and B may be connected together by an interconnect (transmission line). In integrated circuit technology, the interconnect may be exceedingly short, comparable to the device dimension itself. For example, the gates of two transistors may be connected together by polysilicon, or copper interconnect, where the length of the polysilicon, or copper interconnect, is comparable to the gate lengths. As another example, A and B may be connected to each other by a switch, such as a transmission gate, so that their respective voltage potentials are substantially equal to each other when the switch is ON.

It is also to be understood in these letters patent that the meaning of “A is coupled to B” is that either A and B are connected to each other as described above, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element, which in turn is connected to B.

It is also to be understood in these letters patent that a “current source” may mean either a current source or a current sink. Similar remarks apply to similar phrases, such as, “to source current”.

It is also to be understood in these letters patent that various circuit blocks, such as current mirrors, amplifiers, etc., may include switches so as to be switched in or out of a larger circuit, and yet such circuit blocks may still be considered connected to the larger circuit because the various switches may be considered as included in the circuit block. 

1. A circuit comprising: an amplifier to provide an output signal, the amplifier having a tunable peak frequency; a finite state machine, having a set of states, to tune the peak frequency of the amplifier in response to sequencing through states in the set of states; and a control circuit to provide a signal indicative of the difference in amplitudes of the output signal over two consecutive time intervals, and to disable the finite state machine from sequencing through the states when the difference in amplitudes satisfies an ordered relationship with zero.
 2. The circuit as set forth in claim 1, wherein the ordered relationship is satisfied if the difference in amplitudes is less than zero.
 3. The circuit as set forth in claim 1, wherein the output signal is a differential signal.
 4. The circuit as set forth in claim 1, wherein the finite state machine comprises a counter.
 5. The circuit as set forth in claim 1, the amplifier further comprising a tunable reactive load.
 6. The circuit as set forth in claim 5, the tunable reactive load comprising a set of capacitive circuits, the counter having a counter value and coupled to the tunable reactive load so that the capacitance of the tunable reactive load decreases as the counter value decreases.
 7. A circuit comprising: a switched capacitor circuit comprising first and second inverters, each comprising an output port and an input port; first and second switches to respectively connect together the first and second output ports of the first and second inverters when closed; a third switch to connect the input port of the second inverter to the output port of the first inverter when closed, and a fourth switch to connect the input port of the first inverter to the output port of the second inverter when closed; and first and second capacitors, each comprising a first terminal and a second terminal connected to the input ports of the first and second inverters, respectively; and an envelope detector comprising first and second output ports connected to the first terminal of the first and second capacitors, respectively.
 8. The circuit as set forth in claim 7, further comprising: an amplifier to provide a differential output signal to the envelope detector, the amplifier having a tunable peak frequency; and a comparator comprising a first input port connected to the output port of the first inverter, a second input port connected to the output port of the second inverter, and an output port to disable tuning of the amplifier when its output port has a Boolean voltage level.
 9. The circuit as set forth in claim 8, wherein the Boolean voltage level is a HIGH voltage.
 10. The circuit as set forth in claim 8, further comprising a finite state machine, having a set of states, to tune the amplifier in response to sequencing through states in the set of states when enabled, wherein the finite state machine is disabled when the output port of the comparator is at the Boolean voltage level.
 11. The circuit as set forth in claim 8, the amplifier comprising a tunable reactive load.
 12. The circuit as set forth in claim 11, the tunable reactive load comprising a set of capacitor circuits, the finite state machine to change the capacitance of the tunable reactive load in response to sequencing through states in the set of states.
 13. The circuit as set forth in claim 11, wherein the finite state machine comprises a counter having a counter value.
 14. The circuit as set forth in claim 13, the amplifier comprising a reactive load having a capacitance, wherein the capacitance of the reactive load decreases as the counter value decreases.
 15. A circuit comprising: first and second input ports; first and second nodes; a first multiplier to sink current at the first node, the first multiplier coupled to the first input port; a second multiplier to sink current at the first node, the second multiplier coupled to the second input port; a third multiplier to sink current at the second node, the third multiplier coupled to the first input port and the second input port; a fourth multiplier to sink current at the second node, the fourth multiplier coupled to the first input port and the second input port; a first diode-connected transistor comprising a drain coupled to the first node; and a second diode-connected transistor comprising a drain coupled to the second node.
 16. The circuit as set forth in claim 15, further comprising: first and second inverters, each comprising an output port and an input port; first and second switches to respectively connect together the first and second output ports of the first and second inverters when closed; a third switch to connect the input port of the second inverter to the output port of the first inverter when closed, and a fourth switch to connect the input port of the first inverter to the output port of the second inverter when closed; and first and second capacitors, each comprising a first terminal and a second terminal connected to the input ports of the first and second inverters, respectively
 17. The circuit as set forth in claim 15, the first multiplier comprising a first transistor, the first transistor of the first multiplier comprising a gate coupled to the first input port and a source; and a second transistor, the second transistor of the first multiplier comprising a gate coupled to the first input port and a drain connected to the source of the first transistor of the first multiplier; the second multiplier comprising a first transistor, the first transistor of the second multiplier comprising a gate coupled to the second input port and a source; and a second transistor, the second transistor of the second multiplier comprising a gate coupled to the second input port and a drain connected to the source of the first transistor of the second multiplier; the third multiplier comprising a first transistor, the first transistor of the third multiplier comprising a gate coupled to the second input port and a source connected to the drain of the second transistor of the first multiplier; and the fourth multiplier comprising a first transistor, the first transistor of the fourth multiplier comprising a gate coupled to the first input port and a source connected to the drain of the second transistor of the second multiplier.
 18. The circuit as set forth in claim 17, further comprising: first and second inverters, each comprising an output port and an input port; first and second switches to respectively connect together the first and second output ports of the first and second inverters when closed; a third switch to connect the input port of the second inverter to the output port of the first inverter when closed, and a fourth switch to connect the input port of the first inverter to the output port of the second inverter when closed; and first and second capacitors, each comprising a first terminal and a second terminal connected to the input ports of the first and second inverters, respectively.
 19. The circuit as set forth in claim 18, further comprising: a comparator comprising a first input port coupled to the output port of the first inverter, a second input port coupled to the output port of the second inverter, and an output port; an amplifier to provide a first voltage signal to the first input port and a second voltage signal to the second input port, the amplifier having a tunable peak frequency; and a finite state machine, having a set of states, to tune the peak frequency of the amplifier when sequencing through the set of states, wherein the output port of the comparator is coupled to the finite state machine to disable the finite state machine when the output port of the comparator provides a voltage at a Boolean voltage level.
 20. The circuit as set forth in claim 19, wherein the Boolean voltage level is a HIGH voltage level.
 21. The circuit as set forth in claim 19, wherein the finite state machine comprises a counter having a counter value.
 22. The circuit as set forth in claim 21, the amplifier comprising a tunable reactive load having a capacitance, wherein the capacitance of the reactive load decreases as the counter value decreases.
 23. A computer system comprising: a transmission line; a microprocessor comprising a driver to drive the transmission line; a memory; a chipset coupled to the transmission line and to the memory, the chipset comprising: an amplifier to provide an output signal, the amplifier having a tunable peak frequency; a finite state machine, having a set of states, to tune the amplifier in response to sequencing through states in the set of states; and a control circuit to provide a signal indicative of the difference in amplitudes of the output signal at a first time and a second time subsequent to the first time, and to disable the finite state machine from sequencing through the states when the difference in amplitudes satisfies an ordered relationship with zero.
 24. The computer system as set forth in claim 23, wherein the ordered relationship is satisfied if the difference in amplitudes is less than zero.
 25. The computer system as set forth in claim 23, wherein the output signal is a differential signal.
 26. The computer system as set forth in claim 23, wherein the finite state machine comprises a counter.
 27. The computer system as set forth in claim 26, the amplifier comprising a tunable reactive load comprising a set of capacitive circuits, the counter having a counter value and coupled to the tunable reactive load so that the capacitance of the tunable reactive load decreases as the counter value decreases. 